Densification of semiconductor chips to be mounted has been advanced, and hence wiring boards have been required to be thinned, and wiring patterns have been required to be highly densified. To meet these requirements, a so-called coreless board, which is a wiring board from which a core board (supporting member) having high rigidity and thicker than an interlayer insulating film is removed, is proposed (see Japanese Laid-open Patent Application No. 2012-235166, for example). Thus the formed coreless board is manufactured according to, for example, the following manufacturing method.
First, as shown in FIG. 9A, a support substrate 100 is prepared, and a resist layer 101 is formed on the support substrate 100. The resist layer 101 has an opening portion 101X to form a pad P10. The pad P10 including a plating layer (e.g., gold layer/nickel layer) 102 and a wiring layer 103 is formed on the support substrate 100 in the opening portion 101X. Thereafter, at the step of FIG. 9B, the resist layer 101 is removed, and the surface of the wiring layer 103 is subjected to roughening treatment. As a result, the surface of the wiring layer 103 is roughened. Thereafter, at the step of FIG. 9C, an insulating layer 104 is stacked on the support substrate 100 so as to cover the pad P10, and a via hole VH10 that reaches an upper surface 103A of the wiring layer 103 is formed in the insulating layer 104. Thereafter, at the step of FIG. 9D, a via wiring 105 with which the via hole VH10 is filled is formed, and a wiring pattern 106 that is connected to the pad P10 (wiring layer 103) through the via wiring 105 is stacked on the insulating layer 104. Thereafter, as shown in FIG. 9E, insulating layers 107 and 109 and build-up wiring layers 108 and 110 are alternately stacked on the insulating layer 104, and, finally, the support substrate 100 of FIG. 9D is removed.